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| HT82D20R/HT82D20A 27MHz One Channel RX 8-Bit MCU Features * USB specification compliance - Conforms to USB specification V2.0 - Conforms to USB HID specification V1.11 * Supports 1 Low-speed USB control endpoint and * 8-bit RISC microcontroller, with 2K14 bits EPROM (000H~7FFH) * 96 bytes RAM (20H~7FH) * 6MHz internal MCU clock * 4-level stack * Two 7-bit indirect addressing registers * One 16-bit programmable timer counter with 1 interrupt endpoint * Each endpoint has 8 byte FIFO * Integrated USB transceiver * 3.3V regulator output * Built-in one 27MHz FSK receiver * PS2 and USB modes supported * 27MHz FSK receiver power down function * FSK receiver frequency range 26.945~27.295MHz * FSK receiver high sensitivity: < -90 dBm * RF tuner, mixer, transistors, passives, coils, and overflow interrupt (shared with PA7, vector 0CH) * One USB interrupt input (vector 04H) * HALT function and wake-up feature reduce power consumption * PA0~PA7 support wake-up function * Internal power-on reset (POR) * Watchdog Timer (WDT) * 8 I/O ports * 28-pin SSOP package SAW filter functions integrated in the same device * Integrated FSK receiver phase locked loop * Eight user selectable frequencies * Integrated FSK Receiver 6Kbps data rate * Uses external 12MHz crystal General Description USB Encoder Built-in one 27MHz FSK receiver MCU OTP body is suitable for USB interface and 27MHz Wireless system. Flexible total solution for applications that combine PS/2 and low-speed USB interface and 27MHz wireless system, such as mice, joysticks, and many others. It consists of a Holtek high performance 8-bit MCU core for control unit, built-in USB SIE, 27MHz FSK Receiver , 2K14 bits ROM and 96 bytes data RAM. Rev. 1.10 1 January 27, 2010 HT82D20R/HT82D20A Block Diagram U S B D + /C L K U S B D -/D A T A V33O U S B 2 .0 & P S 2 BP In te rru p t C ir c u it STACK P ro g ra m ROM P ro g ra m C o u n te r IN T C TM RL TM RH TM RC M U X fS /4 P A 7 /T M R YS E N /D IS W DTS In s tr u c tio n R e g is te r MP M U X D a ta M e m o ry W D T P r e s c a le r WDT M U X fS YS /4 W DT OSC PAC In s tr u c tio n D ecoder ALU S h ifte r MUX PA PORT A PA0~PA6 P A 7 /T M R P A 1 /F S K _ O U T X T A L _ IN XTAL_O UT T im in g G e n e ra to r STATUS 27M Hz FSK R e c e iv e r A N T _ IN 2 OSCI ACC A N T _ IN 1 Pin Assignment VSS V33O U S B D + /C L K U S B D -/D A T A OSCI RES PA0 P A 1 /F S K _ O U T VSS LF VREF1 VSS A N T _ IN 2 A N T _ IN 1 9 10 11 12 13 14 8 7 6 5 4 3 2 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD P A 7 /T M R PA6 PA2 PA5 PA3 PA4 VSS XTAL_O UT X T A L _ IN VREF3 VCC VREF2 GND H T 8 2 D 2 0 R /H T 8 2 D 2 0 A 2 8 S S O P -A Rev. 1.10 2 January 27, 2010 HT82D20R/HT82D20A Pin Description Pin Name I/O Configuration Option Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by configuration option. The input or output mode is controlled by PAC (PA control register). Pull-high resistor options: PA0~PA7 Pull-low resistor options: PA0~PA3 CMOS/NMOS/PMOS options: PA0~PA7 Falling edge wake-up options: PA0~PA1, PA4~PA7 Rising and falling edge wake-up options: PA2~PA3 PA1 is wire-bonded with FSK demodulated data output The TMR pin is shared with PA7 Digital negative power supply, ground Digital positive power supply Schmitt trigger reset input. Active low. 3.3V regulator output USBD+ or PS2 CLK I/O line USB or PS2 function is controlled by software control register USBD- or PS2 DATA I/O line USB or PS2 function is controlled by software control register Loop filter for Local Oscillator (resistance 24kW and capacity 5.6nF) in parallel with capacity 560pF to ground. For test pin Analog positive power supply Analog negative power supply, ground Mid rail reference voltage for the FSK receiver Internal positive analog supply reference voltage for the FSK receiver Internal positive digital supply reference voltage for the FSK receiver Antenna input 1 Antenna input 2 XTAL_IN, XTAL_OUT are connected to a 12MHz crystal PA0 PA1/FSK_OUT PA2~6 PA7/TMR I/O Pull-low Pull-high Wake-up CMOS/NMOS/PMOS VSS VDD RES V33O USBD+/CLK USBD-/DATA LF OSCI VCC GND VREF1 VREF2 VREF3 ANT_IN1 ANT_IN2 XTAL_IN XTAL_OUT 3/4 3/4 I O I/O I/O I 3/4 I 3/4 O O O I I I O 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...............................0C to 70C Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.10 3 January 27, 2010 HT82D20R/HT82D20A D.C. Characteristics Symbol VDD IDD ISTB1 Parameter Operating Voltage Operating Current Standby Current Test Conditions VDD 3/4 5V 5V Conditions 3/4 No load, fXTAL=12MHz No load, system HALT, USB suspend**, FSK receiver power down No load, system HALT, input/output mode, set SUSPEND2 [1CH].4, FSK receiver power down 3/4 3/4 3/4 3/4 VOL=0.4V VOH=3.4V VOL=0.4V VOH=3.4V 3/4 3/4 3/4 3/4 3/4 Min. 4.0 3/4 3/4 Typ. 3/4 25 1.5 Max. 5.5 3/4 3/4 Ta=25C Unit V mA mA ISTB2 Standby Current 5V 3/4 1.0 3/4 mA VIL1 VIH1 VIL2 VIH2 IOL IOH IOL2 IOH2 RPD RPH1 RPH2 RPH3 VLVR Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) Output Sink Current for PA4~PA7 Output Source Current for PA4~PA7 Output Sink Current for PA0~PA3 Output Source Current for PA0~PA3 Pull-down Resistance for PA0~PA3 Pull-high Resistance for DATA* Pull-high Resistance for CLK Pull-high Resistance for PA0~PA7 Low Voltage Reset 5V 5V 3/4 3/4 5V 5V 5V 5V 5V 3/4 3/4 3/4 3/4 0 2 0 0.9VDD 2 -2.5 10 8 10 1.3 2.0 30 2.4 3/4 3/4 3/4 3/4 4 -4 15 12 30 1.5 4.7 50 2.7 0.8 VDD 0.4VDD VDD 3/4 3/4 3/4 3/4 50 2.0 6.0 70 3 V V V V mA mA mA mA kW kW kW kW V Note: * The DATA pull-high is implemented using an external 1.5kW resister. ** includes 15kW load on the USBD+, USBD- line at the host terminal. Rev. 1.10 4 January 27, 2010 HT82D20R/HT82D20A A.C. Characteristics Symbol fSYS fXTAL Xppm CXTAL fRCSYS tWDT tRF tRES tSST tOSC Parameter System Clock Quartz xtal Frequency Quartz xtal Frequency Tolerance Xtal Shunt Capacitance RC Clock with 8-bit Prescaler Register Watchdog Time-out Period (System Clock) USBD+, USBD- Rising & Falling Time External Reset Low Pulse Width System Start-up Timer Period Crystal Setup Test Conditions VDD 5V 3/4 3/4 3/4 5V 3/4 3/4 3/4 3/4 3/4 Conditions 3/4 3/4 3/4 3/4 3/4 Without WDT prescaler 3/4 3/4 Wake-up from HALT 3/4 Min. 3/4 3/4 3/4 3/4 16 1024 75 1 3/4 3/4 Typ. 6 12 50 47 32 3/4 3/4 3/4 1024 5 Max. 3/4 3/4 3/4 3/4 48 3/4 300 3/4 3/4 10 Ta=25C Unit MHz MHz ppm pF kHz tRCSYS ns ms tSYS ms Note: Power-on period=tWDT+tSST+tOSC WDT Time-out in the normal mode=1/fRCSYS256WDTS+tWDT WDT Time-out in the HALT mode=1/fRCSYS256WDTS+tSST+tOSC RF Characteristics Symbol fCHN Parameter Channel Spacing Test Conditions VCC 5V PB 4 3 2 = 000 001 010 011 100 101 110 111 DC Input Resistance Input Capacitance Antenna Input Sensitivity 5V Differential @27MHz 5V 5V Differential @27MHz Antenna Input 50W to 8kW Impedance Transform 50kHz offset Adjacent Channel Rejection Frequency Deviation Data Rate Internal Mid-rail Reference Internal Supply Voltage Reference Power Up Settling Time 5V 100kHz & 150kHz offsets 5V 5V 5V 5V 5V 3/4 3/4 3/4 3/4 3/4 Conditions 3/4 Min. 3/4 Typ. 50 26.995 27.045 27.095 27.145 27.195 27.245 27.295 26.945 < 100 8 5 3/4 25 28 3/4 6K 1.6 3.3 3 Max. 3/4 Ta=25C Unit kHz fCOM Communication Spacing 5V 3/4 3/4 MHz RIN CIN ASENS ACREJ fDEV DRFSK VREF1 VREF2 tPU 3/4 3/4 3/4 -90 3/4 3/4 3.2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 kW kW pF dbm dB dB kHz bit/sec V V ms Rev. 1.10 5 January 27, 2010 HT82D20R/HT82D20A Functional Description Execution Flow The External crystal must use 12MHZ but the system clock for the microcontroller is derived from 6MHZ internal clock. The system clock is internally divided into four non- overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to be effectively executed in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are S y s te m C lo c k T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading to the PCL register, performing a subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupts, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within the current program ROM page. When a control transfer takes place, an additional dummy cycle is required. O S C 2 ( R C o n ly ) PC PC PC+1 PC+2 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution Flow Program Counter *10 0 0 0 *9 0 0 0 *8 0 0 0 *7 0 0 0 *6 0 0 0 *5 0 0 0 *4 0 0 0 *3 0 0 1 *2 0 1 1 *1 0 0 0 *0 0 0 0 Mode Initial Reset USB Interrupt Timer/Event Counter Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine Program Counter+2 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 Program Counter Note: *10~*0: Program counter bits #10~#0: Instruction code bits S10~S0: Stack register bits @7~@0: PCL bits Rev. 1.10 6 January 27, 2010 HT82D20R/HT82D20A Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 204814 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage: * Location 000H ROM data by two table read instructions: TABRDC and TABRDL, transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). The three methods are shown as follows: The instructions TABRDC [m] (the current page, one page=256words), where the table locations is defined by TBLP (07H) in the current page. And the configuration option TBHP is disabled (default). The instructions TABRDC [m], where the table locations is defined by registers TBLP (07H) and TBHP (01FH). And the configuration option TBHP is enabled. The instructions TABRDL [m], where the table locations is defined by Registers TBLP (07H) in the last page (0700H~07FFH). This area is reserved for program initialization. After a chip reset, the program always begins execution at location 000H. * Location 004H This area is reserved for the USB interrupt service program. If the USB interrupt is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H. * Location 00CH This location is reserved for the Timer/Event Counter interrupt service program. If a timer interrupt results from a Timer/Event Counter overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location 00CH. * Table location Any location in the program memory can be used as look-up tables. There are three method to read the 000H 004H 00CH D e v ic e In itia liz a tio n P r o g r a m U S B In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e P ro g ra m M e m o ry L o o k - u p T a b le ( 2 5 6 W o r d s ) n00H nFFH 7FFH L o o k - u p T a b le ( 2 5 6 W o r d s ) 1 4 B its N o te : n ra n g e s fro m 0 to 7 Program Memory Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 1-bit words are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP, TBHP) is a read/write register (07H, 1FH), which indicates the table location. Before accessing the table, the location must be placed in the TBLP and TBHP (If the configuration option TBHP is disabled, the value in TBHP has no effect). The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending on the requirements. Once TBHP is enabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and TBHP value. Otherwise, the configuration option TBHP is disabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and the current program counter bits. Table Location Instruction TABRDC [m] TABRDL [m] *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0 Table Location Note: *10~*0: Table location bits @7~@0: TBLP bits P10~P8: Current program counter bits when TBHP is disabled TBHP register bit2~bit0 when TBHP is enabled Rev. 1.10 7 January 27, 2010 HT82D20R/HT82D20A Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 4 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 4 return addresses are stored). Data Memory - RAM for Bank 0 The data memory is designed with 968 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (968 bits). Most are read/write, but some are read only. The unused space before 20H is reserved for future expanded usage and reading these locations will get 00H. The general purpose data memory, addressed from 20H to 7FH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer registers (MP0 or MP1). Bank 0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H TBHP USC USR SCC TM RH TM RL TM RC PA PAC PB PBC IA R 0 MP0 IA R 1 MP1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C G e n e ra l P u rp o s e DATA M EM ORY (9 6 B y te s ) 7FH Bank 0 RAM Mapping Rev. 1.10 8 January 27, 2010 HT82D20R/HT82D20A Data Memory - RAM for Bank 1 The special function registers used in the USB interface are located in RAM Bank1. In order to access Bank1 register, only the Indirect addressing pointer MP1 can be used and the Bank register BP should be set to 1. The RAM bank 1 mapping is as shown. Address 00H~1FH in RAM Bank0 and Bank1 are located in the same Registers Bank 1 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 41H 42H 43H 44H 45H 46H 47H 48H 49H TBHP P ip e _ c tr l AW R STALL P IP E S IE S M IS C F IF O F IF O 1 0 USC USR SCC TM RH TM RL TM RC PA PAC PB PBC IA R 0 MP0 IA R 1 MP1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C Indirect Addressing Register Locations 00H and 02H are indirect addressing registers (IAR0:00H; IAR1:02H) that are not physically implemented. Any read/write operation on [00H] ([02H]) will access the data memory pointed to by MP0 (MP1). Reading location 00H (02H) indirectly will return the result 00H. Writing indirectly results in no operation. The indirect addressing pointer (MP0) always points to Bank0 RAM addresses no matter the value of Bank Register (BP). The indirect addressing pointer (MP1) can access Bank0 or Bank1 RAM data according to the value of BP which is set to 0 or 1 respectively. The memory pointer registers (MP0 and MP1) are 7-bit registers. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions: * Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....) The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results from those intended. Bank 1 RAM Mapping Rev. 1.10 9 January 27, 2010 HT82D20R/HT82D20A Bit No. 0 Label C Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Unused bit, read as 0 Status (0AH) Register The TO flag can be affected only by a system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, upon entering the interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at a specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. Function Controls the master (global) interrupt (1=enable; 0=disable) Controls the USB interrupt (1=enable; 0= disable) Unused bit, read as 0 Controls the Timer/Event Counter interrupt (1=enable; 0=disable) USB interrupt request flag (1=active; 0=inactive) Unused bit, read as 0 Internal timer/event counter request flag (1:active; 0:inactive) Unused bit, read as 0 INTC (0BH) Register 1 2 3 4 5 6 7 AC Z OV PDF TO 3/4 3/4 Bit No. 0 1 2 3 4 5 6 7 Label EMI EUI 3/4 ETI USBF 3/4 TF 3/4 Rev. 1.10 10 January 27, 2010 HT82D20R/HT82D20A The USB interrupts are triggered by the following USB events and the related interrupt request flag (USBF; bit 4 of the INTC) will be set. * Access of the corresponding USB FIFO from PC * The USB suspend signal from PC * The USB resume signal from PC * USB Reset signal When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When the PC Host access the FIFO, the corresponding request bit of the USR is set, and a USB interrupt is triggered. So user can easily decide which FIFO is accessed. When the interrupt has been served, the corresponding bit should be cleared by firmware. When the device receives a USB Suspend signal from the Host PC, the suspend line (bit0 of the USC) is set and a USB interrupt is also triggered. When the device receives a Resume signal from the Host PC, the resume line (bit3 of the USC) are set and a USB interrupt is triggered. Whenever a USB reset signal is detected, the USB interrupt is triggered and URST_Flag bit of the USC register is set. When the interrupt has been served, the bit should be cleared by firmware. The internal timer/even counter interrupt is initialized by setting the timer/event counter interrupt request flag (;bit 6 of the INTC), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF is set, a subroutine call to location 0CH will occur. The related interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source USB interrupt Timer/Event Counter overflow Priority 1 2 Vector 04H 0CH Once the interrupt request flags (TF, USBF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. Oscillator Configuration There is an oscillator circuit in the microcontroller. X T A L _ IN 47pF XTAL_O UT 47pF C ry s ta l O s c illa to r System Oscillator This oscillator is designed for system clocks. The HALT mode stops the system oscillator and ignores an external signal to conserve power. A crystal across XTAL_IN and XTAL_OUT is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. In stead of a crystal, a resonator can also be connected between XTAL_IN and XTAL_OUT to get a frequency reference, but two external capacitors in XTAL_IN and XTAL_OUT are required. The external crystal must use 12MHz but it operate in 6MHz system clock. The USB SIE function also operate in 6MHz. Both of XTAL_IN and XTAL_OUT pin must be connect a 47pF capacitor to ground. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works within a period of approximately 31ms. The WDT oscillator can be disabled by configuration option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator), or instruction clock (system clock divided by 4), determine by configuration option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Rev. 1.10 11 January 27, 2010 HT82D20R/HT82D20A S y s te m C lo c k /4 W DT OSC ROM Code O p tio n S e le c t W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r 8 -to -1 M U X W D T T im e - o u t W S0~W S2 Watchdog Timer Timer can be disabled by configuration option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. Once the internal WDT oscillator (RC oscillator with a period of 31ms/5V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of 8ms/5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 1s/5V. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operates in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. The high nibble and bit 3 of the WDTS are reserved for user defined flags, which can only be set to 10000 (WDTS.7~WDTS.3). If the device operates in a noisy environment, using the on-chip 32kHz RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 pending on the configuration option - CLR WDT times selection option. If the CLR WDT is selected (i.e. CLRWDT times is equal to one), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT and CLR WDT are chosen (i.e. CLRWDT times is equal to two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following: * The system oscillator will be turned off but the WDT oscillator remains running (if the WDT oscillator is selected). * The contents of the on-chip RAM and registers remain unchanged. * The WDT and WDT prescaler will be cleared and recounted again (if the WDT clock is from the WDT oscillator). * All of the I/O ports remain in their original status. * The PDF flag is set and the TO flag is cleared. The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the cause for chip reset can be determined. The PDF flag is cleared by a system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and SP; the others remain in their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up func- WDTS (09H) Register The WDT overflow under normal operation will initialize a chip reset and set the status bit TO. But in the HALT mode, the overflow will initialize a warm reset and only the program counter and SP are reset to zero. To clear the contents of the WDT (including the WDT prescaler), three methods are adopted; external reset (a low level to RES), software instruction and a HALT instruction. The software instruction include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active deRev. 1.10 12 January 27, 2010 HT82D20R/HT82D20A tion of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are four ways in which a reset can occur: * RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation * USB reset To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the system resets (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. The functional unit chip reset status are shown below. Program Counter Interrupt Prescaler WDT 000H Disable Clear Clear. After master reset, WDT begins counting Timer/event Counter Off Input/output Ports Stack Pointer Input mode Points to the top of the stack The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the Program Counter and Stack Pointer, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 0 0 1 1 PDF 0 0 0 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT VDD RES S S T T im e - o u t C h ip R eset tS ST Reset Timing Chart HALT W DT RES W a rm R eset Note: u stands for unchanged V DD OSC1 SST 1 0 - b it R ip p le C o u n te r S y s te m R eset C o ld R eset RES Reset Configuration Reset Circuit Rev. 1.10 13 January 27, 2010 HT82D20R/HT82D20A The registers status are summarized in the following table. Reset (Power On) xxxx xxxx xxxx xxxx 00-0 1--000H 1xxx xxxx 1xxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx --00 xxxx -000 0000 1000 0111 1111 1111 1111 1111 1xx1 11xx 1xx1 11xx 11xx 0000 0000 0000 0000 0000 ---- -xxx 0000 0010 0000 0000 0000 0010 0000 0000 0xxx xx00 0x00 0000 xxxx xxxx xxxx xxxx WDT Time-out (Normal Operation) 0000 0000 0000 0000 00-0 1--000H 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --1u uuuu -000 0000 1000 0111 1111 1111 1111 1111 1xx1 11xx 1xx1 11xx uuxx uuuu uuuu uuuu uuuu uuuu ---- -uuu 0000 uuuu uuuu uuuu 0000 uuuu xxxx xxxx uxxx xxuu uxuu uuuu uuuu uuuu uuuu uuuu RES Reset (Normal Operation) 0000 0000 0000 0000 00-0 1--000H 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --uu uuuu -000 0000 1000 0111 1111 1111 1111 1111 1xx1 11xx 1xx1 11xx 11xx 0000 0000 0000 0000 0000 ---- -uuu 0000 0010 0000 0000 0000 0010 0000 0000 0xxx xx00 0x00 0000 uuuu uuuu uuuu uuuu RES Reset (HALT) 0000 0000 0000 0000 00-0 1--000H 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --00 uuuu -000 0000 1000 0111 1111 1111 1111 1111 1xx1 11xx 1xx1 11xx 11xx 0000 0000 0000 0000 0000 ---- -uuu 0000 0010 0000 0000 0000 0010 0000 0000 0xxx xx00 0x00 0000 uuuu uuuu uuuu uuuu WDT Time-Out (HALT)* uuuu uuuu uuuu uuuu uu-u u--000H 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuxx uuuu uuuu uuuu uuuu uuuu ---- -uuu 0000 uuuu uuuu uuuu 0000 uuuu xxxx xxxx uxxx xxuu uxuu uuuu uuuu uuuu uuuu uuuu USB-Reset (Normal) uuuu uuuu uuuu uuuu 00-0 1--000H 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --uu uuuu -000 0000 1000 0111 1111 1111 1111 1111 1xx1 11xx 1xx1 11xx 1100 0u00 u0uu 0000 uu00 u000 ---- -uuu 0000 0010 0000 0000 0000 0010 0000 0000 0xxx xx00 0x00 0000 0000 0000 0000 0000 USB-Reset (HALT) uuuu uuuu uuuu uuuu 00-0 1--000H 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --01 uuuu -000 0000 1000 0111 1111 1111 1111 1111 1xx1 11xx 1xx1 11xx 1100 0u00 u0uu 0000 uu00 u000 ---- -uuu 0000 0010 0000 0000 0000 0010 0000 0000 0xxx xx00 0x00 0000 0000 0000 0000 0000 Register TMRH TMRL TMRC Program Counter MP0 MP1 ACC TBLP TBLH STATUS INTC WDTS PA PAC PB PBC USC USR SCC TBHP PIPE_CTL AWR STALL PIPE SIES MISC FIFO0 FIFO1 Note: * stands for warm reset u stands for unchanged x stands for unknown Rev. 1.10 14 January 27, 2010 HT82D20R/HT82D20A Timer/Event Counter A timer/event counter (TMR) is implemented in the microcontroller. The timer/event counter contains a 16-bit programmable count-up counter and the clock may come from an external source or from the system clock divided by 4. Using the internal clock source, there is only 1 reference time-base for the timer/event counter. The internal clock source is coming from fSYS/4. The external clock input allows the user to count external events, measure time intervals or pulse widths. There are 3 registers related to the timer/event counter; TMRH (0FH), TMRL (10H), TMRC (11H). Writing TMRL will only put the written data to an internal lower-order byte buffer (8 bits) and writing TMRH will transfer the specified data and the contents of the lower-order byte buffer to TMRH and TMRL preload registers, respectively. The timer/event counter preload register is changed by each writing TMRH operations. Reading TMRH will latch the contents of TMRH and TMRL counters to the destination and the lower-order byte buffer, respectively. Reading the TMRL will read the contents of the lower-order byte buffer. The TMRC is the timer/event counter control register, which defines the operating mode, counting enable or disable and active edge. The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, Bit No. 0~2 3 4 5 Label 3/4 TE TON 3/4 Unused bit, read as 0 Defines the TMR active edge of the timer/event counter (0=active on low to high; 1=active on high to low) Enable/disable the timer counting (0=disable; 1=enable) Unused bit, read as 0 Defines the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMRC (11H) Register D a ta B u s fS Y S /4 which means that the clock source comes from an external (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the fSYS/4 (Timer). The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR). The counting is based on the fSYS/4. In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFFFH. Once overflow occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt request flag (TF; bit 6 of the INTC) at the same time. In the pulse width measurement mode with the TON and TE bits equal to one, once the TMR has received a transient from low to high (or high to low if the TE bit is 0) it will start counting until the TMR returns to the original level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON Function 6 7 TM0 TM1 TM R TE TM 1 TM 0 TON TM 1 TM 0 1 6 B its T im e r /E v e n t C o u n te r P r e lo a d R e g is te r L o w B y te B u ffe r R e lo a d P u ls e W id th M e a s u re m e n t M o d e C o n tro l 1 6 B its T im e r /E v e n t C o u n te r (T M R H /T M R L ) O v e r flo w to In te rru p t Timer/Event Counter Rev. 1.10 15 January 27, 2010 HT82D20R/HT82D20A bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in the other two modes the TON can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET can disable the corresponding interrupt services. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. The timer/event counter will still operate until overflow occurs (a timer/event counter reloading will occur at the same time). When the timer/event counter (reading TMR) is read, the clock will be blocked to avoid errors. As clock blocking may result in a counting error, this must be taken into consideration by the programmer. Input/Output Ports There are 8 bidirectional input/output lines in the microcontroller, labeled from PA, which are mapped to the data memory of [12H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC) to control the input/output configuration. With this control register, CMOS/NMOS/PMOS output or Schmitt trigger input with or without pull-high/low resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write a 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the i n t e r n a l b u s. T h e l a t t e r i s p o ssi b l e i n t h e read-modify-write instruction. For output function, CMOS/NMOS/PMOS configurations can be selected. These control registers are mapped to locations 13H. After a chip reset, these input/output lines remain at high levels or in a floating state (depending on the pull-high/low options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. There are pull-high/low options available for I/O lines. Once the pull-high/low option of an I/O line is selected, the I/O line have pull-high/low resistor. Otherwise, the pull-high/low resistor is absent. It should be noted that a non-pull-high/low I/O line operating in input mode will cause a floating state. It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. PA1 is wire-bonded with FSK demodulation data output, if want read FSK demodulation data PA1 must set to input mode. V C o n tr o l B it DD D a ta B u s D PH Q CK S PA0~PA7 Q W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D a ta B it Q D CK S PL M U X P A W a k e - u p O p tio n Q W r ite D a ta R e g is te r P o rt O u tp u t C o n fig u r a tio n R e a d D a ta R e g is te r P A W a k e -u p P A 7 /T M R Input/Output Ports Rev. 1.10 16 January 27, 2010 HT82D20R/HT82D20A Low Voltage Reset - LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device drops to within the range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: * For a valid LVR signal, a low voltage (0.9V~VLVR) must The relationship between VDD and VLVR is shown below. VDD 5 .5 V V OPR 5 .5 V V 2 .7 V 2 .4 V LVR exist for more than 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function. * The LVR uses the OR function with the external 0 .9 V RES signal to perform a chip reset. Note: VOPR is the voltage range for proper chip operation at 6MHz or 12MHz system clock. V 5 .5 V DD V LVR LVR D e te c t V o lta g e 0 .9 V 0V R e s e t S ig n a l R eset *1 N o r m a l O p e r a tio n *2 R eset Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode. Rev. 1.10 17 January 27, 2010 HT82D20R/HT82D20A USB with MCU Interface There are eight registers, including Pipe_ctrl, Address+Remote_WakeUp, STALL, PIPE, SIES, MISC, FIFO 0 and FIFO 1 in this buffer function. Register Name Pipe_ctrl Addr.+Remote Mem. Addr. Reserved Addr. 41H 42H STALL 43H PIPE 44H SIES 45H MISC 46H FIFO 0 48H FIFO 1 49H Bank 1, Address 40H, 4AH, 4FH Register Memory Mapping Address+Remote_WakeUp register represents current address and remote wake-up function. The initial value is 00000000 from MSB to LSB. Register Address 01000010B R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Remote Wake-up Function 0: Not this function 1: The function exists R/W Address value Default value=00000000 Address + Remote_WakeUp Register The Pipe_ctrl, STALL and PIPE are bitmap ones. The Pipe_ctrl Register is used for configuring IN (Bit=1) or OUT (Bit=0) Pipe and only for HT82D20A body. The default is defined as IN Pipe. The PIPE register represents whether the corresponding endpoint is accessed by host or not. After a USB interrupt signal is being sent out, the MCU can check which endpoint had been accessed. This register is set only after the host accessed the corresponding endpoint. The STALL register shows whether the corresponding endpoint works or not. As soon as the endpoint works improperly, the corresponding bit must be set. The bitmaps are listed as follows: Register Name Pipe_ctrl STALL PIPE R/W R/W R/W R Register Address 01000001B 01000011B 01000100B Bit7~Bit2 Reserved 3/4 3/4 3/4 Bit 1 Pipe 1 Pipe 1 Pipe 1 Bit 0 Pipe 0 Pipe 0 Pipe 0 Default Value 00000011 00000000 00000000 STALL (43H) and PIPE (44H) Registers The SIES Register is used to indicate the present signal state which the USB SIE received and also determines whether the USB SIE has to change the device address automatically. Bit No. 7 6~2 1 0 Function MNI Reserved bit F0_ERR Adr_set Read/Write R/W 3/4 R/W R/W SIES (45H) Registers Table 01000101B Register Address Rev. 1.10 18 January 27, 2010 HT82D20R/HT82D20A Function Name Read/ Write Description This bit is used to configure the USB SIE to automatically change the device address with the value of the Address+Remote_WakeUp Register (42H). When this bit is set to 1 by F/W, the USB SIE will update the device address with the value of the Address+Remote_WakeUp Register (42H) after the PC Host has successfully read the data from the device by the IN operation. The USB SIE will clear the bit after updating the device address. Otherwise, when this bit is cleared to 0, the USB SIE will update the device address immediately after an address is written to the Address+Remote_WakeUp Register (42H). This bit is used to indicate when there are some errors that occurred when the FIFO0 is accessed. This bit is set by the USB SIE and cleared by F/W. Bit 2~Bit 6 Reserved bit This bit is for masking the NAK interrupt when MNI=1, the default value=0 SIES Function Table The MISC register is actually a command + status to control the desired FIFO action and to show the status of the desired FIFO. Every bits meaning and usage are listed as follows: Bit No. 7 6 5 4 3 2 1 0 Function Len0 Ready Set CMD Sel_pipe1 Sel_pipe0 Clear Tx Request Read/Write R/W R R/W R/W 01000110B R/W R/W R/W R/W MISC (46H) Registers Table Register Address Adr_set R/W F0_Err 3/4 MNI R/W 3/4 R/W Rev. 1.10 19 January 27, 2010 HT82D20R/HT82D20A Function Name Request Read/Write R/W Description After setting the other desired status, FIFO can be requested by setting this bit high active. After work has been done, this bit must be set low. Represents the direction and transition end of the MCU accesses. When being set as logic 1, the MCU wants to write data to FIFO. After work has been done, this bit must be set to logic 0 before terminating the request to represent a transition end. For reading action, this bit must be set to logic 0 to indicate that the MCU wants to read and must be set to logic 1 after work is done. Represents MCU clear requested FIFO, even if FIFO is not ready. Determines which FIFO is desired, 00 for FIFO 0, 01 for FIFO 1 Shows that the data in FIFO is setup as command. This bit will be cleared by firmware. So, even if the MCU is busy, nothing is missed by the SETUP command from the host. Indicates that the desired FIFO is ready to work. Indicates that the host sent a 0-sized packet to the MCU. This bit must be cleared by a read action to the corresponding FIFO. Also, this bit will be cleared by the USB SIE after the next valid SETUP token is received. MISC Function Table Tx R/W Clear Sel_pipe1 Sel_pipe0 Set CMD Ready Len0 R/W R/W R/W R R/W The devices have two 88 bidirectional FIFO for the two endpoints (control and Interrupt). User can easily read/write the FIFO data by accessing the corresponding FIFO pointer register (FIFO0, FIFO1). The following are two examples for reading and writing the FIFO data: The FIFO is read by packet. To read from FIFO, the following should be followed: * Select one set of FIFO, set in the read mode (MISC The FIFO is written by packet. To write to FIFO, the following should be followed: * Select a set of FIFO, set in the write mode (MISC TX bit = 1), and set the REQ bit to 1 * Check the ready bit until the status = 1 * Write through the FIFO pointer register and take down the data number that has been written * Repeat steps 2 and 3 until writing is complete or the TX bit = 0), and set the REQ bit to 1. * Check the ready bit until the status = 1 * Read through the FIFO pointer register, and record ready bit becomes 0 which indicates that the FIFO no longer allows any data writing. * Set MISC TX bit = 0 * Clear the REQ bit to 0. Complete writing. the data number that has been read. * Repeat steps 2 and 3 until the ready bit becomes 0 which indicates the end of the FIFO data reading. * Set MISC TX bit = 1 * Clear the REQ bit to 0. Complete reading. User reads the data through the FIFO pointer register, user has to record the number of bytes to be read. The devices allow a maximum of 8 bytes of data in each packet. User writes the data through the FIFO pointer register, user has to record the number of bytes that have been written. The devices allow a maximum of 8 bytes of data in each packet. Rev. 1.10 20 January 27, 2010 HT82D20R/HT82D20A There are some timing constrains and usages illustrated here. By setting the MISC register, the MCU can perform reading, writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing and clearing. Actions Read FIFO0 sequence Write FIFO1 sequence Check whether FIFO0 can be read or not Check whether FIFO1 can be written to or not Write 0-sized packet sequence to FIFO 0 MISC Setting Flow and Status 00H(R)01H(R)delay of 2ms, check 41H(R)read* from FIFO0 register and check if not ready (01H)(R)03H(R)02H 0AH(R)0BH(R)delay of 2ms, check 4BH(R)write* to FIFO1 register and check if not ready (0BH)(R)09H(R)08H 00H(R)01H(R)delay of 2ms, check 41H (if ready) or 01H (if not ready)(R)00H 0AH(R)0BH(R)delay of 2ms, check 4BH (if ready) or 0BH (if not ready)(R)0AH 02H(R)03H(R)delay of 2ms, check 43H(R)01H(R)00H Note: *: There are 2ms gap existing between 2 reading actions or between 2 writing actions Register Name FIFO 0 FIFO 1 R/W R/W R/W Register Address 01001000B 01001001B Bit7~Bit0 Data7~Data0 Data7~Data0 FIFO Register Address Table USB Active Pipe Timing The USB active pipe accessed by the host cannot be used by the MCU simultaneously. When the host finishes its work, the signal, a USB_INT will be produced to tell the MCU that the pipe can be used and the acted pipe No. will be shown in the signal, ACT_PIPE as well. The timing is illustrated in the Figure below. A C T _ P IP E U S B _ IN T L a s t A c te d P ip e USB Active Pipe Timing Suspend Wake-Up and Remote Wake-Up If there is no signal on the USB bus for over 3ms, the devices will go into a suspend mode. The Suspend line (bit 0 of the USC) will be set to 1 and a USB interrupt is triggered to indicate that the devices should jump to the suspend state. Disable the USB clock by clearing the USBCKEN (bit3 of the SCC) to 0. The suspend current is 1.5mA. The user want to decrease the suspend current to about 1mA by setting the SUSP2 (bit4 of the SCC). But if the SUSP2 is set, the user has to make sure not to enable the LVR OPT option, otherwise the devices will be reset. When the resume signal is sent out by the host, the devices will wake-up the MCU by USB interrupt and the Resume line (bit 3 of the USC) is set. In order to make the device function properly, the programmer must set the USBCKEN (bit 3 of the SCC) to 1 and clear the SUSP2 (bit4 of the SCC). Since the Resume signal will be cleared before the Idle signal is sent out by the host and the Suspend line (bit 0 of the USC) is going to 0. So when the MCU is detecting the Suspend line (bit0 of the USC), the Resume line should be remembered and taken into consideration. After finishing the resume signal, the suspend line will go inactive and a USB interrupt is triggered. The following is the timing diagram: SUSPEND U S B R e s u m e S ig n a l U S B _ IN T Rev. 1.10 21 January 27, 2010 HT82D20R/HT82D20A The device with remote wake-up function can wake-up the USB Host by sending a wake-up pulse through RMWK (bit 1 of USC). Once the USB Host receive the wake-up signal from the device, it will send a Resume signal to the device. The timing is as follows: SUSPEND M in . 1 U S B C L K RMW K M in .2 .5 m s The user should make sure that in order to read the data properly, the corresponding output bit must be set to 1. For example, if user wants to read the PS2 Data by reading PS2DAI, the PS2DAO should be set to 1. Otherwise it always read a 0. If SPS2=0, and SUSB=1, the device is defined as a USB interface. Both the USBD- and USBD+ are driven by the USB SIE of the device. User only writes or reads the USB data through the corresponding FIFO. Both SPS2 and SUSB default is 0. 27MHz FSK Receiver Function U S B R e s u m e S ig n a l U S B _ IN T To Configure as an PS2 Device The devices can be defined as a USB interface or a PS2 interface by configuring the SPS2 (bit 4 of the USR) and SUSB (bit 5 of the USR). If SPS2=1, and SUSB=0, the device is defined as a PS2 interface, pin USBD- is now defined as PS2 Data pin and USBD+ is now defined as PS2 Clk pin. The user can easily read or write to the PS2 Data or PS2 Clk pin by accessing the corresponding bit PS2DAI (bit 4 of the USC), PS2CKI (bit 5 of the USC), PS2DAO (bit 6 of the USC) and S2CKO (bit 7 of the USC) respectively. There is a single channel integrated RF transceiver designed for human interface devices (HID). Operating at 27MHz, it provide frequency selection from 8 discrete channels via a parallel control bit2~0 [14H].2 ~[14H].4, the frequency range is 26.945~26.995MHz and channel spacing is 50kHz. It provide power down to reduce power consumption by 27MHz FSK Receiver power down bit [14H].7 .The optimized receiver design enables reception up to 3kHz per channel. It supply demodulation output data with PA1. * 27MHz FSK Receiver Control Register 1 (14H) - PB Register Bits 0~1 Labels PB0~PB1 Read/Write 3/4 Reserved bit. Functions 2~4 PB (14H) PB2~PB4 R/W Parallel control bit 2~bit 0 Communication spacing control 000: 26.995 MHz 001: 27.045 MHz 010: 27.095 MHz 011: 27.145 MHz 100: 27.195 MHz 101: 27.245 MHz 110: 27.295 MHz 111: 26.945 MHz Reserved bit. 27MHz FSK Receiver power down bit When 1 indicate FSK Receiver for power down mode, otherwise for normal mode. Default value 0 5~6 PB5~PB6 3/4 7 PB7 R/W * 27MHz FSK Receiver Control Register 2 (15H) - PBC Bit2~bit4 & bit7 must be 0, the other bits are reserved Rev. 1.10 22 January 27, 2010 HT82D20R/HT82D20A I/O Port Special Registers Definition * Port-A (12H) - PA Register Bits 0 Labels PA0 Read/Write R/W Functions I/O (R/W) has pull-low and pull-high configuration option. Has falling edge wake-up configuration option. I/O (R/W) has pull-low and pull-high option. Has falling edge wake-up option. Read FSK demodulation output data for input mode I/O (R/W) has pull-low and pull-high option. Has falling edge and rising edge wake-up option. I/O (R/W) has pull-low and pull-high option. Has falling edge and rising edge wake-up option. I/O (R/W) has pull-high option. Has falling edge wake-up option. I/O (R/W) has pull-high option. Has falling edge wake-up option. I/O (R/W) has pull-high option. Has falling edge wake-up option. I/O (R/W) has pull-high option. Has falling edge wake-up option, pin-shared with timer input pin. 1 PA1 R/W 2 3 4 5 6 7 PA2 PA3 PA4 PA5 PA6 PA7 R/W R/W R/W R/W R/W R/W PA (12H) * Port-A Control (13H) - PAC This port configure the input or output mode of Port-A USB/PS2 Status and Control Register USC (Address 1AH) Register Bits 0 1 2 3 USC (1AH) 4 5 6 7 Labels SUSPEND RMOT_WK URST_FLAG RESUME_O PS2_DAI PS2_CKI PS2_DAO PS2_CKO Read/Write R W R/W R R R W W Functions USB suspend mode status bit. When 1, indicates that the USB system entry is in suspend mode. USB remote wake-up signal. Default value is 0. USB bus reset event flag. Default value is 0. When RESUME_OUT EVENT, RESUME_O is set to 1. Default value is 0. USBD-/DATA input USBD+/CLK input Output for driving USBD-/DATA pin, when working under 3D PS2 mouse function. Default value is 1. Output for driving USBD-/DATA pin, when working under 3D PS2 mouse function. Default value is 1. Rev. 1.10 23 January 27, 2010 HT82D20R/HT82D20A Endpoint Interrupt Status Register USR (Address 1BH) The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select the serial bus (PS2 or USB). The endpoint request flags (EP0IF, EP1IF) are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to 1 and a USB interrupt will occur (If a USB interrupt is enabled and the stack is not full). When the active endpoint request flag is served, the endpoint request flag has to be cleared to 0. Register Bits Labels Read/Write Functions When set to 1, indicates an endpoint 0 interrupt event. Must wait for the MCU to process the interrupt event and clear this bit by firmware. This bit must be 0, then the next interrupt event will be processed. Default value is 0. When set to 1, indicates an endpoint 1 interrupt event. Must wait for the MCU to process the interrupt event, then clear this bit by firmware. This bit must be 0, then the next interrupt event will be processed. Default value is 0. Reserved bit, set to 0 When set to 1, indicates that the chip is working under PS2 mode. Default value is 0. When set to 1, indicates that the chip is working under USB mode. Default value is 0. Reserved bit, set to 0 This flag is used to show that the MCU is in USB mode (Bit=1). This bit is R/W by FW and will be cleared to zero after power-on reset. The default value is 0. 0 EP0IF R/W 1 EP1IF R/W USR (1BH) 2~3 4 5 6 7 3/4 SELPS2 SELUSB 3/4 USB_flag R/W R/W R/W R/W R/W Clock Control Register SCC (Address 1CH) There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB clock control bit (USBCKEN), second suspend mode control bit (SUSPEND2). Register Bits 2~0 3 Labels 3/4 USBCKEN Read/Write R/W R/W Reserved USB clock control bit. When set to 1, indicates a USBCK ON, else USBCK OFF. Default value is 0. This bit is used to reduce power consumption in the suspend mode. In the normal mode this bit must be cleared to zero(De fault=0). In the HALT mode this bit should be set high to reduce power consumption and LVR with no function. In the USB mode this bit cannot be set high. Reserved Reserved bit, set to 1 This flag is used to show that the MCU is in PS2 mode (Bit=1). This bit is R/W by FW and will be cleared to zero after power-on reset. The default value is 0. Functions 4 SCC (1CH) 5 6 7 SUSPEND2 R/W 3/4 3/4 PS2_flag R/W R/W R/W Note: The user must set bit 6 in the SCC register high after a power-on reset. Rev. 1.10 24 January 27, 2010 HT82D20R/HT82D20A Table High Byte Pointer for Current Table Read TBHP (Address 1FH) Register TBHP (1FH) Bits 2~0 Labels 3/4 Read/Write R Functions Store current table read bit10~bit8 data Configuration Options No. 1 2 3 4 5 6 7 8 9 WDT clock source: RC or fSYS/4 (default: fSYS/4) WDT clock source: enable/disable for normal mode (default: disable) PA0~PA7 wake-up by bit (PA2, PA3 both wake-up by falling or rising edge) (default: non wake-up) PA0~PA7 pull-high by bit (default: Pull-high) 2.7 V (error 0.3V) LVR enable/disable (default: enable) PA0~PA3 pull-low by bit (default: non pull-low) CLR WDT, 1 or 2 instructions TBHP enable/disable (default: disable) PA output mode (CMOS/NMOS/PMOS) by bit (default: CMOS) Option The LVR voltage is define as 2.7V0.3V and default is enable. Application Circuits Crystal for Multiple I/O Applications Note: The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. Components with * are used for EMC issue. Rev. 1.10 25 January 27, 2010 HT82D20R/HT82D20A Instruction Set Introduction C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Rev. 1.10 26 January 27, 2010 HT82D20R/HT82D20A Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m] Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Logic Operation Increment & Decrement Rev. 1.10 27 January 27, 2010 HT82D20R/HT82D20A Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.10 28 January 27, 2010 HT82D20R/HT82D20A Instruction Definition ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z Rev. 1.10 29 January 27, 2010 HT82D20R/HT82D20A CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Operation Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation Affected flag(s) CLR WDT1 Description Operation Affected flag(s) CLR WDT2 Description Operation Affected flag(s) Rev. 1.10 30 January 27, 2010 HT82D20R/HT82D20A CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF Operation Affected flag(s) DAA [m] Description Operation Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description Operation Affected flag(s) Rev. 1.10 31 January 27, 2010 HT82D20R/HT82D20A INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s) Rev. 1.10 32 January 27, 2010 HT82D20R/HT82D20A OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Affected flag(s) RETI Description Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None Operation Affected flag(s) RL [m] Description Operation Affected flag(s) RLA [m] Description Operation Affected flag(s) Rev. 1.10 33 January 27, 2010 HT82D20R/HT82D20A RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C Affected flag(s) RLCA [m] Description Operation Affected flag(s) RR [m] Description Operation Affected flag(s) RRA [m] Description Operation Affected flag(s) RRC [m] Description Operation Affected flag(s) RRCA [m] Description Operation Affected flag(s) Rev. 1.10 34 January 27, 2010 HT82D20R/HT82D20A SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None Operation Affected flag(s) SBCM A,[m] Description Operation Affected flag(s) SDZ [m] Description Operation Affected flag(s) SDZA [m] Description Operation Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s) Rev. 1.10 35 January 27, 2010 HT82D20R/HT82D20A SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C Operation Affected flag(s) SIZA [m] Description Operation Affected flag(s) SNZ [m].i Description Operation Affected flag(s) SUB A,[m] Description Operation Affected flag(s) SUBM A,[m] Description Operation Affected flag(s) SUB A,x Description Operation Affected flag(s) Rev. 1.10 36 January 27, 2010 HT82D20R/HT82D20A SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Affected flag(s) SZ [m] Description Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Operation Affected flag(s) SZA [m] Description Operation Affected flag(s) SZ [m].i Description Operation Affected flag(s) TABRDC [m] Description Operation Affected flag(s) TABRDL [m] Description Operation Affected flag(s) Rev. 1.10 37 January 27, 2010 HT82D20R/HT82D20A XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z Rev. 1.10 38 January 27, 2010 HT82D20R/HT82D20A Package Information 28-pin SSOP (150mil) Outline Dimensions 28 A 15 B 1 C C' 14 G H = F D E Symbol A B C C D E F G H a Dimensions in mil Min. 228 150 8 386 54 3/4 4 22 7 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 244 157 12 394 60 3/4 10 28 10 8 Rev. 1.10 39 January 27, 2010 HT82D20R/HT82D20A Product Tape and Reel Specifications Reel Dimensions T2 D A B C T1 SSOP 28S (150mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 62.01.5 13.0 +0.5/-0.2 2.00.5 16.8 +0.3/-0.2 22.20.2 Rev. 1.10 40 January 27, 2010 HT82D20R/HT82D20A Carrier Tape Dimensions D E F P0 P1 t W C B0 D1 P A0 K0 R e e l H o le p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e . IC SSOP 28S (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 16.00.3 8.00.1 1.750.1 7.50.1 1.55 1.50 +0.10/-0.00 +0.25/-0.00 4.00.1 2.00.1 6.50.1 10.30.1 2.10.1 0.300.05 13.30.1 Rev. 1.10 41 January 27, 2010 HT82D20R/HT82D20A Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright O 2010 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 42 January 27, 2010 |
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